In a typical serializer/deserializer (SerDes) system, a transmitter circuit is coupled to a receiver circuit. A serial data stream is transmitted from the transmitter circuit via transmission lines, which may be referred to collectively as a transmission channel, that connect the transmitter circuit to the receiver circuit.
As an example, an integrated circuit such as a field programmable gate array (FPGA) device or an application specific integrated circuit (ASIC) device, may include transceiver circuitry that includes both transmitter and receiver circuits. Signals may be transmitted from logic blocks within the integrated circuit device (e.g., the core region of the device) to the transmitter circuit to be transmitted out of the integrated circuit device. Accordingly, signals received by the receiver circuit may be transmitted to the core region or other parts of the integrated circuit device for further processing.
When signals are propagated from one circuit to another (e.g., from a transmitter circuit to a receiver circuit, or from one integrated circuit device to another), there may be signal loss due to numerous reasons (e.g., resistance in the transmission channel, etc.). As such, the received signals are distorted and may need to be reconstructed (or equalized) before they are processed or used by other circuitry.
Generally, an equalizer is included in transmitter and receiver circuits to equalize signals that are being transmitted between different circuits or devices. However, the equalizer circuit typically only supports a limited range of data rates and as such may only be applicable to limited applications that fall within that range. It is within this context that the embodiments described herein arise.